1. Field of the Invention
The invention relates generally to semiconductor packages and manufacturing methods thereof. More particularly, the invention relates to a wafer level semiconductor package and manufacturing methods thereof.
2. Description of Related Art
Semiconductor devices have become progressively more complex, driven at least in part by the demand for smaller sizes and enhanced processing speeds. To support increased functionality, semiconductor packages including these devices often have an large number of contact pads for external electrical connection, such as for inputs and outputs. These contact pads can occupy a significant amount of the surface area of a semiconductor package.
In the past, wafer level packaging could be restricted to a fan-in configuration in which electrical contacts and other components of a resulting semiconductor device package can be restricted to an area defined by a periphery of a semiconductor device. To address the increasing number of contact pads, wafer level packaging is no longer limited to the fan-in configuration, but can also support a fan-out configuration. For example, in a fan-out configuration, contact pads can be located at least partially outside an area defined by a periphery of a semiconductor device. The contact pads may also be located on multiple sides of a semiconductor package, such as on both a top surface and a bottom surface of the semiconductor package.
However, forming and routing the electrically connections from a semiconductor device to this increasing number of contact pads can result in greater process complexity and cost. It is against this background that a need arose to develop the wafer level semiconductor package and related methods described herein.